Piton
Junior Member
Posts: 94
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Post by Piton on Mar 17, 2022 19:25:03 GMT
My hardware Only PC, USB-UART (based cp2102). RTS signal is used to control high voltage.  |
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Post by dino2gnt on Mar 17, 2022 19:29:33 GMT
The CSM also ignores additional commands while an erase is in progress:
Correct or not, it works. I have an ECU on my bench that I have repeatedly erased and written test patterns to while developing this.
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Piton
Junior Member
Posts: 94
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Post by Piton on Mar 17, 2022 19:42:37 GMT
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Piton
Junior Member
Posts: 94
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Post by Piton on Mar 17, 2022 20:18:44 GMT
There are bugs in the custom code.
For example
utility ldErase
ROM:02CC Check_Ready: ; CODE XREF: LdErase+1Ap
ROM:02CC ; LdErase+24p ...
ROM:02CC jsr Set_TimeOut
ROM:02D0 ldab #0Ah ; number of attempts
ROM:02D2 stab tmp_variable
ROM:02D6
ROM:02D6 not_ready: ; CODE XREF: Check_Ready+2Aj
ROM:02D6 brclr 7922h, Z, #10h, chk_Ready ; Check Flag Timeout
ROM:02DC jsr Set_TimeOut ; new attempt
ROM:02E0 decw tmp_variable ; decrement number of attempts
ROM:02E4 bne chk_Ready
ROM:02E6 ldab #80h ; return error "not ready"
ROM:02E8 bra Exit
ROM:02EA ; ---------------------------------------------------------------------------
ROM:02EA
ROM:02EA chk_Ready: ; CODE XREF: Check_Ready:not_readyj
ROM:02EA ; Check_Ready+18j
ROM:02EA ldd #70h ; CMD Read Status Register
ROM:02EE std 0, X
ROM:02F0 ldd 0, X ; Read Status registr
ROM:02F2 andd #80h ; check Flag Ready
ROM:02F6 beq not_ready ; no,repeat check flag
ROM:02F8 ldd 0, X ; else
ROM:02FA andd #78h ; Check for other errors in the status register.
ROM:02FE
ROM:02FE Exit: ; CODE XREF: Check_Ready+1Cj
ROM:02FE rts
ROM:02FE ; End of function Check_Ready
Set variable as byte
ROM:02D0 ldab #0Ah ; number of attempts
ROM:02D2 stab tmp_variable
Decrement variable as word
ROM:02E0 decw tmp_variable ; decrement number of attempts
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Post by dino2gnt on Mar 17, 2022 21:49:32 GMT
I noticed that in the stock ldErase worker, too. I originally copied that timer-loop code including using ldab #byte_value / stab memory_word / decw memory_word and while it functioned, I felt the same way about mixing byte accesses and word accesses and changed it all to use rD instead.
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Piton
Junior Member
Posts: 94
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Post by Piton on Mar 17, 2022 22:25:38 GMT
Tested code for all cases.
;==============================
;Subr Erase
;Address within the block being erased
;XK:IX Addres
ERASE:
ldab #20 ;Time Out 20 Sec
stab TimeOut
bsr INITGPT
bsr NEWTIME
LPERASE:
jsr CLRSTAT
ldd #$20 ; CMD erase
std 0,X ; Bank address
ldd #$D0 ; CMD erase confirm
std 0,X
LPREADY:
brclr $7922,Z,#$10,FREADY
bsr NEWTIME
dec TimeOut
beq RD_STAT ;Read Status & return subr
FREADY:
bsr RD_STAT
tba
anda #80h ; Check fReady
beq LPREADY ; wait fReady
andb #78h ; Check
bne LPERASE ; other error
;============================
;Subr
;Read Status Register
RD_STAT:
ldd #$70 ;CMD
std 0,X
ldd 0,X ; Return Status register
rts
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